Quartus II 错代码集合（不断整理中）

#由于语法错误引起的一大堆 错，此处是因为if语句后只能执行一条命令，如果要执行多条命令，必须加begin-end；
{
Error (10170): Verilog HDL syntax error at half_adder.v(13) near text “=”; expecting “.”, or “(”

Error (10759): Verilog HDL error at half_adder.v(14): object in_2 declared in a list of port declarations cannot be redeclared within the module body

Error (10759): Verilog HDL error at half_adder.v(17): object in_2 declared in a list of port declarations cannot be redeclared within the module body

Error (10759): Verilog HDL error at half_adder.v(20): object in_2 declared in a list of port declarations cannot be redeclared within the module body

Error (10112): Ignored design unit “half_adder” at half_adder.v(1) due to previous errors
}
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#检查是不是某个变量名打错了
Error (10161): Verilog HDL error at half_adder.v(27): object “sun” is not declared

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#模块名用到的不对
Error (12007): Top-level design entity “adder” is undefined

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#Quartus工程中新加入的模块需要将相应的可综合文件add到工程下才能综合。
Error (12006): Node instance “half_adder_inst0” instantiates undefined entity “half_adder”