leading ATPG tools: Mentor Graphics Fast ScanSynopsys TetraMAXand more.
Complete translation solution integrated into Verigy’s SmarTest operating
system: Optimized support for all V93000 digital cards and test processor controlled power supplies (Ce/P, Pin Scale 400/800/3600/HX, DC Scale DPS32/VI32/UHC4); full support for x-modes (maximizing vector memory utilization), multi-port (concurrent testing), multi clock domain, and pattern synchronous DC (Vbump, Iddx); and better tester resource utilization through timing, waveforms, and levels reuse (incremental mode).
Get the most out of your V93000 with SmarTest Data Link:
Full loop back to simulation for cyclized test vectors or post processed V93000 binariesSupport for most common EDA standards
Advanced EDA and ATE
capabilities without changes to the conversion process
The full power of the V93000’s test processor-per-pin architecture-enabling per-pin-resources for digital and DC channelsIntegrated support for Verigy Yield Learning solutions and SCAN Pattern based data logging
Integrated solution for program
creation from EDA to the V93000. Pin configuration,
levels, timing and vector generation for fastest TTM and optimized tester resource utilization
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